1. Field of the Invention
The invention relates generally to semiconductor memory devices and, more particularly, relates to semiconductor memory devices in which increased integration density is achieved by preventing destruction of data stored in memory cells due to injection of electrons.
2. Description of the Background Art
One example of a conventional semiconductor memory device will be described in the following, referring to FIG. 1. FIG. 1 shows a structure of a DRAM (Dynamic Random Access Memory) including a CMOS (Complementary Metal Oxide Semiconductor), employing an n-channel MOS field-effect transistor and a p-channel MOS field-effect transistor (refer to "IEEE Journal of Solid-State Circuit Vol. 24, No. 5, October 1989, p1170-p1174"). The DRAM has an n-well 2 and p-well 3 formed on a p-type semiconductor substrate 1. The n-well 2 is connected to a power supply voltage V.sub.CC that is applied to an n-type impurity region 4 therein and the p-well 3 is connected to a substrate voltage V.sub.BB that is applied to a p-type impurity region 5 therein. A p-channel MOS field-effect transistor (hereinafter referred to as "pMOSFET") 6 is formed on the surface of the n-well 2 and two n-channel MOS field-effect transistors (hereinafter referred to as "nMOSFET") 7a, 7b are formed on the surface of the p-well 3.
The pMOSFET 6 includes p-type impurity diffusion regions 8 as source and drain regions and a gate electrode 10 formed over a channel region between the p-type impurity diffusion regions 8 with a gate oxide film 9 interposed therebetween. The nMOSFETs 7a, 7b include n-type impurity diffusion regions 11a, 11b as source and drain regions and gate electrodes 13a and 13b over channel regions between the n-type impurity diffusion regions 11a and 11b and respectively with gate oxide films 12a, 12b interposed therebetween. In the general CMOS circuit structured in such a way, the source electrode S1 of the pMOSFET 6 is connected to the power supply voltage level V.sub.CC terminal and the source electrode S.sub.2 of the nMOSFET is connected to the ground terminal at the potential of a ground level V.sub.SS. The nMOSFET 7b is one memory cell among a multiplicity of memory cells and has the gate electrode 13b to be a word line (WL) and the two n-type impurity diffusion regions 11b connected to a storage node (SN) which is a charge-storage electrode and a bit line (BL) which is a read/write electrode respectively. Another cross section of the memory cell is shown in FIG. 3A and an equivalent circuit thereof is shown in FIG. 3B. A thick oxide film 14 selectively formed on the semiconductor substrate 1 provides insulation between diffusion regions.
The operation of the semiconductor memory device structured as stated above will now be described. Generally, a negative potential of the order of -3 V is, for example, supplied as a substrate potential V.sub.BB. The reason for it is as follows. When an externally applied input signal is supplied to the n-type impurity diffusion regions 11a formed in the p-well 3, the potential V.sub.BB of the p-well 3 sometimes becomes higher than the potential of the n-type impurity diffusion region 11a because of the undershoot when the signal changes from an H level to an L level and because of the negative potential being supplied as the input of the L level, where undershoot occurs in which the voltage attains a negative level for a undershoot is indicated by an arrow A in FIG. 2 where an external signal is supplied to a terminal and changes, for example, from 5 V to 0 V as shown in the figure. Therefore, when V.sub.BB is 0 V, the pn junction of the n-type impurity diffusion regions 11a and the p-well 3 becomes forward biased, so that electrons are injected. The electrons are injected in the direction from the n-type impurity diffusion regions 11a to the p-well, so that the injected electrons reach the memory cell and destroy the data in the memory cell. The negative potential V.sub.BB, is supplied in order to prevent such an injection of electrons.
As miniaturization of the gate electrodes 10, 13a, and 13b is advanced in devices with a larger storage capacity, however, there occurs a problem that the dielectric strength between the source and drain of the transistor is reduced by the negative potential, i.e., the substrate potential. That is, application of a negative voltage to the p-well 3 increases the threshold voltages of the nMOSFETs 7a, 7b. When the concentration of the p-type impurities of the channel is decreased in order to control the increase in the threshold voltages, the depletion layer tends to be expanded in the channel and punch through occurs between the source and drain, so that the dielectric strength between the source and drain is decreased. Therefore, there is a problem that it is difficult to miniaturize the transistor as far as the negative potential is supplied to the substrate potential.